An Energy-Efficient Design Paradigm for a Memory Cell Based on Novel Nanoelectromechanical Switches

In this chapter, we explain NEMsCAM cell, a new content-addressable memory (CAM) cell, which is designed based on both CMOS technologies and nanoelectromechanical (NEM) switches. The memory part of NEMsCAM is designed with two complementary nonvolatile NEM switches and located on top of the CMOS-based comparison component. As a use case, we evaluate first-level instruction and data translation lookaside buffers (TLBs) with 16 nm CMOS technology at 2 GHz. The simulation results demonstrate that the NEMsCAM TLB reduces the energy consumption per search operation (by 27%), standby mode (by 53.9%), write operation (by 41.9%), and the area (by 40.5%) compared to a CMOS-only TLB with minimal performance overhead

NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs

In this paper we propose a novel Content Addressable Memory (CAM) cell, NEMsCAM, based on both Nano-electro-mechanical (NEM) switches and CMOS technologies. The memory component of the proposed CAM cell is designed with two complementary non-volatile NEM switches and located on top of the CMOS-based comparison component. As a use case for the NEMsCAM cell, we design first-level data and instruction Translation Lookaside Buffers (TLBs) with 16nm CMOS technology at 2GHz. The simulations show that the NEMsCAM TLB reduces the energy consumption per search operation (by 27%), write operation (by 41.9%) and standby mode (by 53.9%), and the area (by 40.5%) compared to a CMOS-only TLB with minimal performance overhead.We thank all anonymous reviewers for their insightful comments. This work is supported in part by the European Union (FEDER funds) under contract TIN2012-34557, and the European Union’s Seventh Framework Programme (FP7/2007-2013) under the ParaDIME project (GA no. 318693)Postprint (author's final draft

DAPHNE: An Open and Extensible System Infrastructure for Integrated Data Analysis Pipelines

Integrated data analysis (IDA) pipelines—that combine data management (DM) and query processing, high-performance computing (HPC), and machine learning (ML) training and scoring—become increasingly common in practice. Interestingly, systems of these areas share many compilation and runtime techniques, and the used—increasingly heterogeneous—hardware infrastructure converges as well. Yet, the programming paradigms, cluster resource management, data formats and representations, as well as execution strategies differ substantially. DAPHNE is an open and extensible system infrastructure for such IDA pipelines, including language abstractions, compilation and runtime techniques, multi-level scheduling, hardware (HW) accelerators, and computational storage for increasing productivity and eliminating unnecessary overheads. In this paper, we make a case for IDA pipelines, describe the overall DAPHNE system architecture, its key components, and the design of a vectorized execution engine for computational storage, HW accelerators, as well as local and distributed operations. Preliminary experiments that compare DAPHNE with MonetDB, Pandas, DuckDB, and TensorFlow show promising results

Improving the performance and energy-efficiency of virtual memory

Virtual memory improves programmer productivity, enhances process security, and increases memory utilization. However, virtual memory requires an address translation from the virtual to the physical address space on every memory operation. Page-based implementations of virtual memory divide physical memory into fixed size pages, and use a per-process page table to map virtual pages to physical pages. The hardware key component for accelerating address translation is the Translation Lookaside Buffer (TLB), that holds recently used mappings from the virtual to the physical address space. However, address translation still incurs high (i) performance overheads due to costly page table walks after TLB misses, and (ii) energy overheads due to frequent TLB lookups on every memory operation. This thesis quantifies these overheads and proposes techniques to mitigate them. In this thesis we argue that fixed size page-based approaches for address translation exhibit limited potential for improving TLB performance because they increase the TLB reach by a fixed amount. To overcome the limitations of such approaches, we introduce the concept of range translations and we show how they can significantly improve the performance and energy-efficiency of address translation. We first comprehensively quantify the address translation performance overhead on a collection of emerging scale-out applications. We show that address translation accounts for up to 16% of the total execution time. We find that huge pages may improve the application performance by reducing the time spent in page walks, enabling better exploitation of the available execution resources. However, the limited hardware support for huge pages in combination with the workloads' low memory locality leave ample space for performance optimizations. To reduce the performance overheads of address translation, we propose Redundant Memory Mappings (RMM). RMM provides an efficient alternative representation of many virtual-to-physical mappings. We define a range translation be a subset of a process's pages that are virtually and physically contiguous. RMM translates each range translation with a single range table entry, enabling a modest number of entries to translate most of the process's address space. RMM operates in parallel with standard paging and introduces a software range table and a hardware range TLB with arbitrarily large reach that is accessed in parallel with the regular L2-page TLB. We modify the operating system to automatically detect ranges and to increase their likelihood with eager paging. RMM is thus transparent to applications. We prototype RMM software in Linux and emulate the hardware. RMM reduces the overhead of virtual memory to less than 1% on average on a wide range of workloads. To reduce the energy cost of address translation, we propose the Lite mechanism and the TLB-Lite and RMM-Lite designs. Lite monitors the performance and utility of L1 TLBs, and adaptively changes their sizes with way-disabling. The resulting TLB-Lite design targets commodity processors with TLB support for huge pages and opportunistically reduces the dynamic energy spent in address translation with minimal impact on TLB miss cycles. To further provide more energy-efficient address translation, we propose RMM-Lite that adds to RMM an L1-range TLB, that is accessed in parallel with the regular L1-page TLB, and the Lite mechanism. The high hit ratio of the L1-range TLB allows Lite to downsize the L1-page TLBs more aggressively. RMM-Lite reduces the dynamic energy spent in address translation by 71% on average. Above the near-zero L2 TLB misses from RMM, RMM-Lite further reduces the overhead from L1 TLB misses by 99\%. The proposed designs target current and future high-performance and energy-efficient memory systems to meet the ever increasing memory demands of applications.La memoria virtual aumenta la productividad del programador, provee seguridad a los procesos e incrementa la utilización de la memoria. No obstante, la memoria virtual requiere de una traducción de direcciones entre los espacios de direcciones virtual y físico en cada operación de memoria. La implementación de la memoria virtual paginada divide la memoria física en páginas de tamaño fijo. El principal componente para acelerar la traducción de direcciones es la TLB (Translation Lookaside Buffer). Sin embargo, la traducción de direcciones tiene un alto coste en el rendimiento, por la necesidad de buscar en la tabla de páginas después de un fallo de TLB, y por el coste energético por las frecuentes búsquedas en la TLB (una por cada operación de memoria). En esta tesis defendemos que los mecanismos de traducción basados en páginas tienen un potencial limitado para aumentar el rendimiento de la TLB. Principalmente porque solo se puede aumentar en una cantidad limitada el conjunto de direcciones que la TLB puede traducir. Para superar esta limitaciones, introducimos el concepto de traducciones por rangos y mostramos como este mecanismo puede mejorar significativamente el rendimiento y la eficiencia energética en la traducción de direcciones. Primero, cuantificamos la pérdida de rendimiento debido a la traducción en aplicaciones emergentes que escalan bien al agregar más procesadores. Mostramos que en estas aplicaciones la traducción de direcciones es responsable de hasta el 16% del tiempo de ejecución. Además, también mostramos que las páginas grandes pueden mejorar el rendimiento de las aplicaciones, permitiendo un mejor uso de los recursos disponibles. Sin embargo, el limitado soporte del hardware para páginas grandes, combinado con cargas de trabajo con poca localidad, nos deja mucho espacio para la optimización. Para reducir los costes de rendimiento de la traducción de direcciones, proponemos RMM (Redundant Memory Mappings). RMM esta basado en rangos de páginas y ofrece una vía alternativa eficiente para representar muchas traducciones. Definimos un rango de traducción como un subconjunto de páginas contiguas de un proceso, tanto en el espacio virtual como en el físico. RMM traduce con un pequeño número de rangos la mayor parte del espacio de direcciones del proceso, y opera en paralelo con el sistema estándar de paginación, agregando una tabla de rangos implementada en software y una TLB de rangos de dimensión arbitraria, accedida en paralelo por la TLB de segundo nivel. Modificamos el sistema operativo para que automáticamente detecte los rangos y aumente su probabilidad de uso. RMM es un mecanismo transparente a las aplicaciones y reduce la pérdida de rendimiento de la memoria virtual hasta algo menos del 1% de media. Para reducir los costes energéticos en la traducción de direcciones, diseñamos el mecanismo Lite, e introducimos los diseños TLBLite y RMMLite. Lite monitora el rendimiento y la utilización de la TLB de primer nivel y adapta su tamaño apagando vías. TLBLite esta orientado a los procesadores actuales que soportan páginas grandes. TLBLite reduce el consumo de energía dinámica usado en la traducción de direcciones, con un impacto mínimo de ciclos en los fallos de TLB. Para hacer aún más eficiente energéticamente la traducción de direcciones proponemos RRMLite, el cual agrega a RMM una TLB de rango paralela a la TLB de primer nivel que tiene el mecanismo Lite. El alto ratio de aciertos en la RMM de primer nivel nos permite deshabilitar vías de la TLB de primer nivel de forma agresiva. RMMLite reduce la energía dinámica total utilizada para la traducción de direcciones en un promedio del 71%. Las técnicas propuestas están diseñadas para soportar sistemas de memoria de alto rendimiento, además de ser eficientes energéticamente, y por lo tanto podrán ser usadas tanto por las aplicaciones actuales como para las futuras que incrementarán su requerimiento a memoria

Protection of patients’ data in e-Health systems: A concise review for Greece and Europe

E-health is a new reality in healthcare and medicine. It is a field that is starting to find application mainly in developed economies but not only. The complexity of modern systems poses new challenges in the management of information and also requires the development of legislation to safeguard citizens. This article highlights this need in a comparative approach setting Greece as a case study in the European environment. Being an ever-growing sector, it is deemed that this system will play a catalytic role in national economies in the following years. At the same time, this essay provides a presentation of current legislation concerning health data protection in Europe and Greece, presented both individually and comparatively. Finally, it examines if further supplements to the current legislation are needed, aiming for higher health data protection levels concerning millions of people involved, either voluntarily or not, in e-health. Keywords: e-Health, European Union, Greece, Health Data, Health Data protection DOI: 10.7176/PPAR/12-2-06 Publication date: May30th 202

Analyzing the Correlations and the Statistical Distribution of Moderate to Large Earthquakes Interevent Times in Greece

Seismic temporal properties constitute a fundamental component in developing probabilistic models for earthquake occurrence in a specific area. Earthquake occurrence is neither periodic nor completely random but often accrues into bursts in both short- and long-term time scales, and involves a complex summation of triggered and independent events (ΔT). This behavior underlines the impact of the correlations on many potential applications such as the stochastic point process for the earthquake interevent times. In this respect, we intend firstly to determine the appropriate magnitude thresholds, Mthr, indicating the temporal crossover between correlated and statistically independent earthquakes in each 1 of the 10 distinctive sub-areas of the Aegean region. The second goal is the investigation of the statistical distribution that optimally fits the interevent times’ data for earthquakes with M≥Mthr after evaluating the Gamma, Weibull, Lognormal and Exponential distributions performance. Results concerning the correlations analysis evidenced that the temporal crossover of the earthquake interevent time data ranges from Mthr≥ 4.7 up to Mthr≥ 5.1 among the 10 sub-areas. The distribution fitting and comparison reveals that the Gamma distribution outperforms the other three distributions for all the data sets. This finding indicates a burst or clustering behavior in the earthquake interevent times, in which each earthquake occurrence depends upon only the occurrence time of the last one and not from the full seismic history